Comparison between the dynamic performance of double-and single-gate AlInAs/InGaAs HEMTs

Publicado por

Colecciones : GIDS. Artículos del Grupo de Investigación en Dispositivos Semiconductores
Fecha de publicación : 2007
Se han estudiado las características estáticas y dinámicas de HEMTs de doblre puerta (DG-HEMTs) por medio de simulaciones Monte Carlo, y se han comparado con las de los HEMTs de puerta única. Las simulaciones reproducen adecuadamente los resultados experimentales y permiten confirmar y explicar desde el punto de vista microscópico el origen de la reducción de los efectos de canal corto y el aumento de fmax que se observa en los transistores de doble puerta.The static and dynamic behavior of InAlAs/InGaAsdouble-gate high-electron mobility transistors (DG-HEMTs) isstudied by means of an ensemble 2-D Monte Carlo simulator.The model allows us to satisfactorily reproduce the experimentalperformance of this novel device and to go deeply into its physicalbehavior. A complete comparison between DG and similarstandard HEMTs has been performed, and devices with differentgate lengths have been analyzed in order to check the attenuationof short-channel effects expected in the DG-structures. Wehave confirmed that, for very small gate lengths, short-channeleffects are less significant in the DG-HEMTs, leading to a betterintrinsic dynamic performance. Moreover, the higher values ofthe transconductance over drain conductance ratio gm/gd and,especially, the lower gate resistance Rg also provide a significantimprovement of the extrinsic fmax.
Publicado el : lunes, 20 de agosto de 2012
Lectura(s) : 24
Fuente : Gredos de la universidad de salamenca
Licencia: Más información
Atribución, No Comercial, Compartir bajo la misma forma idéntica
Número de páginas: 8
Ver más Ver menos
irohtuAcelid zese uednsbrFeryuaedadn  o ta 2:70 ,2 9002 to: IEE limited .oDnwol EpXoler
Comparison Between the Dynamic Performance of Double- and Single-Gate AlInAs/InGaAs HEMTs Beatriz G. Vasallo, Nicolas Wichmann, Sylvain Bollaert, Yannick Roelens, Alain Cappy, Senior Member, IEEE , Tomás González, Senior Member, IEEE , Daniel Pardo, and Javier Mateos
Abstract —The static and dynamic behavior of InAlAs/InGaAs double-gate high-electron mobility transistors (DG-HEMTs) is studied by means of an ensemble 2-D Monte Carlo simulator. The model allows us to satisfactorily reproduce the experimental performance of this novel device and to go deeply into its phys-ical behavior. A complete comparison between DG and similar standard HEMTs has been performed, and devices with different gate lengths have been analyzed in order to check the attenua-tion of short-channel effects expected in the DG-structures. We have confirmed that, for very small gate lengths, short-channel effects are less significant in the DG-HEMTs, leading to a better intrinsic dynamic performance. Moreover, the higher values of the transconductance over drain conductance ratio g m /g d and, especially, the lower gate resistance R g also provide a significant improvement of the extrinsic f max . Index Terms —Double-gate high-electron mobility transistor (DG-HEMT), dynamic behavior, Monte Carlo (MC) simulations. I. I NTRODUCTION ility transistors (HEMTs) I hnaPv-eBAprSoEvDedhtioghe-xehliebcittroannemxocbellentperformanceforap-(FLiigl.le1,.FraSnEceM).imageofa100-nm-gateDG-HEMTfabricatedintheIEMN plications in the microwave and millimeter-wave frequency ranges [1]. To further improve the frequency operation of these microwave performance of the HEMTs. To avoid these effects, devices, their gate length L g has been reduced down to the tech-nological limit. In this way, a cutoff frequency f t of 562 GHz a vertical scaling of the layer structure must go along with the and a maximum oscillation frequency f max of 330 GHz have r L e g d / u a ct,iownheorfeth a eigsattheelednisgttahnicneobredtewretoenketheepagahtiegehleacstpreocdteraatniod been obtained in a T-gate InAlAs/InGaAs pseudomorphic the 2-D channel electron gas. This scaling rule is limited by the HEMT by reducing L g down to 25 nm [2]. The reduction of emergence of a leakage current through the Schottky barrier the source and drain parasitic resistances by using a multilayer captechnologyina30-nm-gate-lengthstructureallowedusto8att1h0engmat.e;Ththeun,s, f t t hcisandnisottasnccaelecaunpnaotnybmeorreeduwciethdt L o g .leTsshethdaen-reach an f max of 400 GHz, together with a simultaneously high f t of 547 GHz [3]. However, very small values of L g involve vice aspect ratio is consequently considered as the fundamental theso-calledshort-channeleffects(thegatecapacitancedoeslimTitookfeHepEoMnTis.mprovingthefrequencyperformanceofthese not scale with L g anymore, and the transconductance g m and transistors (especially regarding f max ), alternative solutions the output conductance g d are deteriorated), which limit the based on an evolution of the standard HEMT design have been considered. Thus, the double-gate HEMT (DG-HEMT), which is a HEMT with two gates placed on each side of the conducting Manuscript received April 5, 2007; revised July 5, 2007. This work was [I4n]Ga[6A].sEcvheannnieflt(hsieseidFeiag.w1a)s,choanscebieveendsreocmeentltiydevegloopfeod supported in part by the Dirección General de Investigación (MEC, Spain) and me a r FEDER through the Project TEC2004-05231 and in part by the Consejería sh e first de Educación of the Junta de Castilla y León (Spain) through the Project tSiim-deetvoiceosur[7k]no[9w]l,etdhgee,atuhtehofrasbriinca[t4i]on[6o]fDoGw-t,rafnosristthorson SA044A05. This work has been performed in the framework of Institut de III–V materials. In those previous works [4]–[6], we have Recherche en Composants pour l’Information et la Communication Avancée (IRCICA). The review of this paper was arranged by Editor M. Anwar. -HEMT which B. G. Vasallo, T. González, D. Pardo, and J. Mateos are with the Departa-reexphiobrtitesdathveefraybrhiicgahtioexntroifnsaic10 g 0 m -namndT-agagteooDdGpinchoff,behav-mento de Física Aplicada, Universidad de Salamanca, 37008 Salamanca, Spain ior (lower g d ) as compared with the conventional single-gate (e-mail:; N. Wichmann, S. Bollaert, Y. Roelens, and A. Cappy are with the Institut e de d’Electronique, de Microélectronique et de Nanotechnologies–Département (aSbGe)t-teHrEcMhaTr.gTehicsohnatrpoplnasndsinccoeutnhteeraDctGsgtehoemeeftfreyctcaonfpcraorvriier Hyperfréquences et Semiconducteurs, 59652 Villeneuve d’Ascq, France. Digital Object Identifier 10.1109/TED.2007.907801 injection into the buffer (since no buffer is used in the structure). 0018-9383/$25.00 © 2007 IEEE
y.plaps XploEEE om I2 fritnortciR seer .
timit deI :o EEElid nsce ued lseAtuohirez
II. P HYSICAL M ODEL For the calculations, we make use of a semiclassical en-semble MC simulator, self-consistently coupled with a 2-D Poisson solver whose validity has been previously checked for Fig. 2. Schematic drawing of the simulated SG- and DG-HEMTs. conventional HEMTs [10]–[12]. The model takes into account important physical effects, as the influence of degeneracy in III. C OMPARISON B ETWEEN E XPERIMENTAL the electron accumulation appearing in the channel by using the rejection technique [10]. The schemes of the DG- and AND MC R ESULTS SG-device topologies used in the simulations are shown in In order to carry out the comparison of the measured results Fig. 2. They are a recessed In 0 . 52 Al 0 . 48 As / In 0 . 53 Ga 0 . 47 As (extrinsic) with those obtained from the simulation (intrinsic), it DG-HEMT and the corresponding standard SG-HEMT. The is necessary to include, in a postprocessing stage, the parasitic layer structure is similar to that of the 100-nm-gate fabricated elements that are not considered in the intrinsic MC model. transistors [5], [6] to establish a correspondence with the exper- Thus, drain ( R D met ) and source ( R S met ) parasitic resistances imental measurements. associated with metallizations have been incorporated into the Our MC algorithm allows us to analyze transistors with dif- original MC results, with the best fit being obtained for R m D et = ferent gate lengths (the experimental one, where L g = 100 nm, 0.15 · mm and R S met = 0.10 · mm, which are found to and the shorter ones, where L g = 25 and 50 nm) to check the coincide in both devices. By separately adjusting the surface attenuation of short-channel effects expected for DG-devices charge at the cap layer and at the bottom of the recess ( 6.2 × with respect to standard SG-HEMTs. In order to provoke im- 10 16 and 4.3 × 10 16 m 2 , respectively), the static characteris-portant short-channel effects and thus facilitate the study, the tics of the experimental 100-nm-gate DG- and SG-HEMTs [5] scaling down of the vertical dimensions is not performed when can be very nicely reproduced by our MC simulator, as shown reducing L g from 100 to 50 and 25 nm (the vertical thicknesses in Fig. 3. of the different layers are kept the same). Regarding the dynamic behavior of the HEMTs, Fig. 4 With regard to the dynamic behavior, the same intrinsic shows the comparison between the experimental and the MC SSEC is considered for both types of devices [10]–[13]. This values of the main intrinsic SSEC parameters ( g m , g d , C gs , is correct as long as the DG-HEMT works in a common and C gd ) for the 100-nm-gate DG- and SG-HEMTs, where mode, i.e., the potential applied at both gate electrodes ( V GS1 = V DS = 0.5 V. For the calculation of the MC results, in order V GS2 = V GS ) is identical. The SSEC is calculated, taking to extract the actual intrinsic SSEC, the access resistances as a basis the Y -parameters, obtained by using the typical corresponding to the ohmic regions near the source and drain MC technique [13]. After that, the intrinsic cutoff frequency electrodes R a S cc and R acc respectively, are removed from the D , f C is calculated as g m / 2 πC gs . Finally, having established a raw simulated values. The values for these parameters are correspondence between measurements and MC results, the extracted from the experimental measurements (in the 100-nm-experimental parasitic elements can be taken into account in the gate devices) of the total parasitic resistances R e S xp and R e D xp SSEC for the correct calculation of the extrinsic f t and f max . by subtracting the resistances of metallizations, providing the
In order to better understand the intrinsic performance and to provide a theoretical model for this brand-new device, we present a complete study of In 0 . 52 Al 0 . 48 As / In 0 . 53 Ga 0 . 47 As DG-HEMT structures carried out by means of a semiclassical 2-D ensemble Monte Carlo (MC) simulator [10]–[12]. Our model allows us to satisfactorily reproduce the static and dy-namic performances of the experimental DG-HEMT presented in [5] and [6], thus confirming its validity for the simulation of DG-devices. It also provides a fully microscopic interpretation of the differences in the static and dynamic performances of the DG-HEMT, in comparison with a similar standard SG-HEMT. In addition, devices with different L g are simulated to verify the expected attenuation of short-channel effects in DG-devices. This paper is organized as follows. In Section II, the phys-ical model employed in the analysis is described. Later, the comparison between the experimental and simulated 100-nm DG- and SG-HEMTs, both of static characteristics and small signal equivalent circuit (SSEC) parameters, is presented in Section III in order to validate our model. In Section IV, the MC results for the 100- and 50-nm-gate-length devices are shown. Finally, in Section V, the most important conclusion of this paper is drawn.
ciitno s .R sertreloXpE EE Iomfr 22:70 ta 9002 ,ry 2bruan Feed ooldaoDnwer .pXol
ecil dezirohtuAeditim lse uednsoler EpXI EEt :o on adedwnlo. Do ,2 9002rbeFyraufr2  Iomt  a:207er .R seEE EpXols apply.triction
SG-transistors. The discrepancy in the values of g d for high V GS can be attributed to the experimental frequency dispersion due to traps and other layer defects which are not included in the MC model. It seems that, in a dynamic operation, the devices are more resistive, so that the stationary bias point, which is in the saturated region of the I V curves, may be shifted to the linear part of the characteristics (providing the increase of g d for high V GS ). Indeed, the static value of g d is well reproduced by the simulations, as confirmed by the satisfactory agreement of the I V curves [Fig. 3(a) and (b)]. On the other hand, MC simulations somewhat underestimate the values of C gs , mainly in the DG-HEMT (even if the agreement can be considered reasonable up to V GS = 0.2 V). The cause for this discrepancy can again be the not-considered layer defects. We remark that experimental Hall measurements show a degrada-tion of the mobility in the channel of the DG-HEMTs. This fact, together with the common overestimation of the electron velocity given by the ideal MC model [10]–[12], means that the electron concentration in the simulations fitting the experi-mental values of I d and g m is probably lower than the real one (mainly in the DG-HEMT), which can also lead to lower values of C gs .
IV. MC C OMPARISON B ETWEEN DG-AND SG-HEMTs The simulated extrinsic output characteristics for 100- and 50-nm-gate DG (where V GS1 = V GS2 = V GS ) and SG-HEMTs with a device width of W = 100 µ m are shown in Fig. 5. The drain current provided by the DG-HEMTs is about twice that given by the SG-transistors (as shown in Fig. 3). This occurs because the electron concentration in the DG-HEMT channel is significantly higher than in the conventional HEMT (for both values of L g ) due to the presence of two charge-accumulation regions. This can be appreciated in Fig. 6, where the electron density profile along the vertical direction under the gate of the Fig. 3. Comparison of the extrinsic I D V DS curves measured in fabricated 100-nm DG- and SG-HEMTs is presented ( V DS = 0.5 V and 1si0m0-unlamti-ognatoef(sai)mDilGar-adnevdic(ebs).STGh-eHgEatMeTvsolwtaitghetohfosteheotbotapinceudrvfersomisth V e GS MC = V GS = 0.1 V). 0.0 V, and the step of the gate bias is V GS = 0.1 V for both sets of curves. The immunity to short-channel effects in the static charac-(c) Corresponding I D V GS curves for V DS = 0.5 V. teristics achieved with the DG-architecture is confirmed by the results shown in Fig. 7, which reports the behavior of the thresh-following: R S acc = R e S xp R S met = 0.08 · mm and R a D cc = old voltage ( V T , calculated by extrapolating to zero current R e D xp R m D et = 0.11 · mm in the DG-HEMT and R a S cc = the I D versus V GS plot) when shortening L g . In Fig. 7(a), 0.23 · mm and R a D cc = 0.22 · mm in the SG-HEMT. The it is observed that the V T roll-off is less pronounced in the same values are used for the 50-nm-gate devices. Note that DG-structure than in the SG-one. Drain-induced barrier low-the access resistances are lower for the DG-HEMT than for the ering (DIBL, calculated as the difference between the values of SG-device due to the higher carrier concentration. V T for V DS = 1.0 and 0.5 V) is also reduced in the DG-device, In addition, it is necessary to include the so-called “ex- as shown in Fig. 7(b). Regarding subthreshold swing, the value ternal” geometric capacitances between the contact accesses experimentally found in the DG-structure (75 mV/dec) is much C gesxt and C gexdt (extracted from the comparison of the results lower than in the SG-HEMT (125 mV/dec) for the 100-nm-of the simulations at I D = 0 with the experimental measure- gate devices. This parameter cannot reliably be calculated ments, as explained in [10] and [11]). The values obtained with MC simulations because of the extremely low current for the 100-nm-gate devices (which will also be used for the level. 50-nm ones since the same layout is considered) are the fol- With regard to the dynamic behavior of the transistors, Fig. 8 lowing: C gesxt = 280 fF/mm and C gexdt = 255 fF/mm for the shows that the MC values of g m are notably higher in the DG-HEMT and C gesxt = 210 fF/mm and C gexdt = 152 fF/mm for DG than in the conventional HEMT due to the approximately the SG-HEMT. double charge in the channel. When decreasing L g , an increase In general, we find a good agreement between the experi- of g m would be expected, but this does not happen. This is due mental and the MC results for g m and C gd for both DG- and to the nonoptimized layer structure of the 50-nm-gate devices.
loadDownn Feed oyr2 rbau90a  ,022 :207t EE IomfrerolpX ErtseR  .ictions apply.
Fig. 4. Experimental and MC values of (a) and (c) g m and g d , and (b) and (d) C gs and C gd versus V GS for the 100-nm-gate (a) and (b) DG- and (c) and (d) SG-HEMTs. V DS = 0.5 V.
identintismoreev,TofwrihehGSH-MEseeaheswgmchcrde,gLglihwdernnicustepdtheV,an=0.1issbeaigetafohthosshi.T1V0.S=VGtceffelennahc-trdnGSH-MEsThttaraeshowninFig.2.ThtageloveegattroftoheurpcsiveGSsVisocrtnictahtuuperisractforttics001)a(eh(dna-mn-m--n50b)-aDGtega.g.5CMxeiFnedfbtaieSG-orth.shTEHTMtca,siafeslbilswtelawnhotsdael,rorpminaovedvalueoffmax.Atuohirez dilecsn ued lseitim tedI :o EEEolpX .ergramgiehfohacestducegdinowerndalihgihylemertxenaedadlounicnsrintiagn/mdgovtlgageHEMTs,whintheDG-ahterhtnihciromsnthatohatieestmeetaicerpthtobnidseeacrinapisgdincunirndeeuotLgdgofdeypesswheviceahc-lenneffe.stceethannhdscerthotahtcemoibenedffItisnoticeabletheDthrehe,w1V0.=SGVotputsaelta()onanreginearhelicathpporTMas-GEHthtobseas)seue,dniylaercsdgdprahtures.AnosestrucffrenihtneecfoubtegaAns.heotmprievortnemrtnicudoontrolachievedbyhtpeerescnoetfowofontiucchhi,wgdinwohssib(8.giFnthenedbyviceewdeteyregmoredesihtottotagmdna,behtstubteraore(esthsTT.ehotdnGSH-MEttheleftpgateisaV1.0=SGVdnaV5.0ecrghadcveromp.istdiirhgttehi)asVDS=aph.hegreoft6.T.arsnevsrlarpbleproofoftheFigtitssetumeraakra.TTssrhiulesontcde01lutaGDa--0mnatefthegesimorthtartnecnrednunoielofleocoontrecchisaclesame,whitaletyehparpxomiemtrnsaiHEG-,iMTfoesDehttnieaceh-HEMinDGectsleffnaen-thchsronofotiuaenttdateecxpeehtfoecnedivera
¡Sé el primero en escribir un comentario!

13/1000 caracteres como máximo.